The present invention relates to a semiconductor memory storage, and in particular to a random-access semiconductor memory storage comprising a memory cell array having a plurality of memory cells arranged in a matrix, a plurality of word line drivers each connected through the corresponding one of a plurality of word lines to the corresponding one of a plurality of the memory cells arranged in a row in the memory cell array for activating a selected word line as the result of decoding an address signal, and a sense amplifier for detecting the activated state of the memory cells.
A semiconductor memory storage is known which has a circuit for correcting the effect of variations in production conditions for forming a memory cell array on a silicon substrate, and variations of the environmental temperature conditions and voltage conditions.
FIG. 5 is a circuit diagram schematically showing the conventional semiconductor memory storage. This semiconductor memory storage comprises a memory cell array 2 with a plurality of memory cells 1 arranged in a matrix, and a word line driver 4 for activating a word line selected in accordance with the result of address decoding by a pre-decoder 3. A plurality of the memory cells 1 arranged in a column are connected to a corresponding sense amplifier 6 through a pair of bit lines 5. Further, a replica column 7 of the memory cells 1 is arranged beside the memory cell array 2, and the gate of the pass transistor of each replica memory cell 8 is connected to an address logic circuit 9 through a dummy word line 10. Furthermore, a dummy bit line 11 connected with a predetermined number of the replica memory cells 8 is connected to the sense amplifier 6 as a signal line for an enable signal.
In this configuration, an input address is decoded by the address logic circuit 9 and a given one of the word line drivers 4, a specified memory cell 1 is selected, and the selected memory 1 generates a potential difference between the pair of bit lines 5. Also, the gates of the pass transistors of a predetermined number of the replica memory cells 8 are activated through the dummy word line 10 from the address logic circuit 9. Further, an enable signal for the sense amplifier 6 is generated on the dummy bit line 11 through the column I/O logic circuit 12. The sense amplifier 6 that has received the enable signal detects the potential difference generated between the pair of bit lines 5.
In the conventional semiconductor memory storage device described above, the signal path for activating the memory cells and the signal path for activating the sense amplifier are separated from each other. Specifically, the word line selected through the word line driver 4 from the pre-decoder 3 and the dummy bit line 11 from the address logic circuit 9 through the replica memory cell 8 and the column I/O logic circuit 12 are separate from each other. Since these two signal lines are separate from each other, the accuracy of the timing at which the word line is actually activated is low. Therefore, in order to avoid a malfunction, a considerable margin is required for the timing of the enable signal for the sense amplifier. Also, the use of a replica memory cell having a similar configuration to the memory cells in the replica column leads to a redundant circuit configuration including the accompanying column I/O logic circuit 12, thereby posing the problem of an area overhead.